SIHD5N50D features ?optimal design - low area specific on-resistance - low input capacitance (c iss ) - reduced capa citive switching losses - high body diode ruggedness - avalanche energy rated (uis) ? optimal efficiency and operation - low cost - simple gate drive circuitry - low figure-of- merit (fom): r on x q g - fast switching ? material categorization: for definitions of compliance please see applications ? consumer electronics - displays (lcd or plasma tv) ? server and telecom power supplies - smps ? industrial - welding - induction heating - motor drives ? battery chargers notes a. repetitive rating; puls e width limited by maximum junction temperature. b. v dd = 50 v, starting t j = 25 c, l = 2.3 mh, r g = 25 ? , i as = 4.5 a. c. 1.6 mm from case. d. i sd ? i d , starting t j = 25 c. product summary v ds (v) at t j max. 550 r ds(on) max. at 25 c ( ? )v gs = 10 v 1.5 q g (max.) (nc) 20 q gs (nc) 3 q gd (nc) 5 configuration single n-channel mosfet g d s dpak (to-252) s d g ordering information package dpak (to-252) lead (pb)-free SIHD5N50D-e3 lead (pb)-free and halogen-free SIHD5N50D-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 gate-source voltage ac (f > 1 hz) 30 continuous drain current (t j = 150 c) v gs at 10 v t c = 25 c i d 5.3 a t c = 100 c 3.4 pulsed drain current a i dm 10 linear dera ting factor 0.83 w/c single pulse avalanche energy b e as 23 mj maximum power dissipation p d 104 w operating junction and storage temperature range t j , t stg - 55 to + 150 c drain-source voltage slope t j = 125 c dv/dt 24 v/ns reverse diode dv/dt (d) 0.28 soldering recommendations (peak temperature) c for 10 s 300 c d series power mosfet www.freescale.net.cn www.freescale.net.cn 1 / 9 SIHD5N50D www.vishay.com vishay siliconix s12-0690-rev. a, 02-apr-12 1 document number: 91499 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 d series power mosfet features ?optimal design - low area specific on-resistance - low input capacitance (c iss ) - reduced capa citive switching losses - high body diode ruggedness - avalanche energy rated (uis) ? optimal efficiency and operation - low cost - simple gate drive circuitry - low figure-of- merit (fom): r on x q g - fast switching ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? consumer electronics - displays (lcd or plasma tv) ? server and telecom power supplies - smps ? industrial - welding - induction heating - motor drives ? battery chargers notes a. repetitive rating; puls e width limited by maximum junction temperature. b. v dd = 50 v, starting t j = 25 c, l = 2.3 mh, r g = 25 : , i as = 4.5 a. c. 1.6 mm from case. d. i sd d i d , starting t j = 25 c. product summary v ds (v) at t j max. 550 r ds(on) max. at 25 c ( : )v gs = 10 v 1.5 q g (max.) (nc) 20 q gs (nc) 3 q gd (nc) 5 configuration single n-channel mosfet g d s dpak (to-252) s d g ordering information package dpak (to-252) lead (pb)-free SIHD5N50D-e3 lead (pb)-free and halogen-free SIHD5N50D-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 gate-source voltage ac (f > 1 hz) 30 continuous drain current (t j = 150 c) v gs at 10 v t c = 25 c i d 5.3 a t c = 100 c 3.4 pulsed drain current a i dm 10 linear dera ting factor 0.83 w/c single pulse avalanche energy b e as 23 mj maximum power dissipation p d 104 w operating junction and storage temperature range t j , t stg - 55 to + 150 c drain-source voltage slope t j = 125 c dv/dt 24 v/ns reverse diode dv/dt (d) 0.28 soldering recommendations (peak temperature) c for 10 s 300 c
notes a. repetitive rating; puls e width limited by maximum junction temperature. b. c oss(er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 % to 80 % v dss . c. c oss(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v dss . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w maximum junction-to-case (drain) r thjc -1.2 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 250 a - 0.58 - v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 3 - 5 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 1 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 10 drain-source on-state resistance r ds(on) v gs = 10 v i d = 2.5 a - 1.2 1.5 ? forward transconductance a g fs v ds = 20 v, i d = 2.5 a - 1.8 - s dynamic input capacitance c iss v gs = 0 v, v ds = 100 v, f = 1 mhz - 325 - pf output capacitance c oss -34- reverse transfer capacitance c rss -6- effective output capacitance, energy related b c o(er) v ds = 0 v to 400 v, v gs = 0 v -31- effective output capacitance, time related c c o(tr) -41- total gate charge q g v gs = 10 v i d = 2.5 a, v ds = 400 v -1020 nc gate-source charge q gs -3- gate-drain charge q gd -5- turn-on delay time t d(on) v dd = 400 v, i d = 2.5 a r g = 9.1 ? , v gs = 10 v -1224 ns rise time t r -1122 turn-off delay time t d(off) -1428 fall time t f -1122 gate input resistance r g f = 1 mhz, open drain - 1.7 - ? drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --5 a pulsed diode forward current i sm --20 diode forward voltage v sd t j = 25 c, i s = 4 a, v gs = 0 v - - 1.2 v reverse recovery time t rr t j = 25 c, i f = i s = 2.5 a, di/dt = 100 a/s, v r = 20 v - 320 - ns reverse recovery charge q rr -1.2-c reverse recovery current i rrm -8-a s d g SIHD5N50D d series power mosfet www.freescale.net.cn 2 / 9 SIHD5N50D www.vishay.com vishay siliconix s12-0690-rev. a, 02-apr-12 2 document number: 91499 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. repetitive rating; puls e width limited by maximum junction temperature. b. c oss(er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 % to 80 % v dss . c. c oss(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v dss . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w maximum junction-to-case (drain) r thjc -1.2 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient ' v ds /t j reference to 25 c, i d = 250 a - 0.58 - v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 3 - 5 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 1 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 10 drain-source on-state resistance r ds(on) v gs = 10 v i d = 2.5 a - 1.2 1.5 : forward transconductance a g fs v ds = 20 v, i d = 2.5 a - 1.8 - s dynamic input capacitance c iss v gs = 0 v, v ds = 100 v, f = 1 mhz - 325 - pf output capacitance c oss -34- reverse transfer capacitance c rss -6- effective output capacitance, energy related b c o(er) v ds = 0 v to 400 v, v gs = 0 v -31- effective output capacitance, time related c c o(tr) -41- total gate charge q g v gs = 10 v i d = 2.5 a, v ds = 400 v -1020 nc gate-source charge q gs -3- gate-drain charge q gd -5- turn-on delay time t d(on) v dd = 400 v, i d = 2.5 a r g = 9.1 : , v gs = 10 v -1224 ns rise time t r -1122 turn-off delay time t d(off) -1428 fall time t f -1122 gate input resistance r g f = 1 mhz, open drain - 1.7 - : drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --5 a pulsed diode forward current i sm --20 diode forward voltage v sd t j = 25 c, i s = 4 a, v gs = 0 v - - 1.2 v reverse recovery time t rr t j = 25 c, i f = i s = 2.5 a, di/dt = 100 a/s, v r = 20 v - 320 - ns reverse recovery charge q rr -1.2-c reverse recovery current i rrm -8-a s d g
typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 0 3 6 9 12 t j = 25 c top 15 v 14 v 13 v 12 v 11 v 10 v 9 v 6 v 7 v 8 v 0 5 10 15 20 25 30 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 2 01020 0 8 4 6 t j = 150 c 5152530 top 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8.0 v 7.0 v 6.0 v 5.0 v v gs , gate-to-source voltage (v) i d , drain-to-source current (a) 010 25 51520 0 3 6 9 12 t j = 150 c t j = 25 c t j , junction temperature (c) r d s (on) , drain-to- s ource 2.5 0.5 - 60 3 2 1.5 1 0 - 40 - 20 0 20 40 60 80 100 120 140 160 v gs = 10 v i d = 2.5 a on re s i s tance (normalized) 1 10 100 1000 0 100 200 300 400 500 v d s , drain-to- s ource voltage (v) capacitance (pf) c i ss c o ss c r ss v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd 0 3 6 9 12 15 18 q g , total g ate charge (nc) v gs , g ate-to- s ource voltage (v) 16 4 0 24 v d s = 400 v v d s = 250 v v d s = 100 v 20 12 8 SIHD5N50D d series power mosfet www.freescale.net.cn 3 / 9 SIHD5N50D www.vishay.com vishay siliconix s12-0690-rev. a, 02-apr-12 3 document number: 91499 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 0 3 6 9 12 t j = 25 c top 15 v 14 v 13 v 12 v 11 v 10 v 9 v 6 v 7 v 8 v 0 5 10 15 20 25 30 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 2 01020 0 8 4 6 t j = 150 c 5152530 top 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8.0 v 7.0 v 6.0 v 5.0 v v gs , gate-to-source voltage (v) i d , drain-to-source current (a) 010 25 51520 0 3 6 9 12 t j = 150 c t j = 25 c t j , junction temperature (c) r d s (on) , drain-to- s ource 2.5 0.5 - 60 3 2 1.5 1 0 - 40 - 20 0 20 40 60 80 100 120 140 160 v gs = 10 v i d = 2.5 a on re s i s tance (normalized) 1 10 100 1000 0 100 200 300 400 500 v d s , drain-to- s ource voltage (v) capacitance (pf) c i ss c o ss c r ss v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd 0 3 6 9 12 15 18 q g , total g ate charge (nc) v gs , g ate-to- s ource voltage (v) 16 4 0 24 v d s = 400 v v d s = 250 v v d s = 100 v 20 12 8
fig. 7 - typical source-dra in diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain curre nt vs. case temperature fig. 10 - typical drain-to-source voltage vs. temperature fig. 11 - normalized thermal transient impedance, junction-to-case v s d , s ource-drain voltage (v) i s d , rever s e drain current (a) 0.1 1 10 100 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t j = 150 c t j = 25 c v gs = 0 v v d s , drain-to- s ource voltage (v) i d , drain current (a) 0.01 0.1 1 10 100 1 10 100 1000 * v gs > minimum v gs at which r d s (on) i s s pecied operation in thi s area limited by r d s (on) bvd ss limited t c = 25 c t j = 150 c s ingle pul s e limited by r d s (on) * 100 s 1 m s 10 m s t j , case temperature (c) i d , drain current (a) 25 50 75 100 125 150 1 2 3 4 5 6 0 t j , junction temperature (c) v ds , drain-to-source - 60 0 160 brakdown voltage (v) - 40 - 20 20 40 60 80 100 120 140 475 500 525 550 575 600 625 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective tran s ient thermal impedance pul s e time ( s ) duty cycle = 0.5 0.1 0.05 s ingle pul s e 0.2 0.02 SIHD5N50D d series power mosfet www.freescale.net.cn 4 / 9 SIHD5N50D www.vishay.com vishay siliconix s12-0690-rev. a, 02-apr-12 4 document number: 91499 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical source-dra in diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain curre nt vs. case temperature fig. 10 - typical drain-to-source voltage vs. temperature fig. 11 - normalized thermal transient impedance, junction-to-case v s d , s ource-drain voltage (v) i s d , rever s e drain current (a) 0.1 1 10 100 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t j = 150 c t j = 25 c v gs = 0 v v d s , drain-to- s ource voltage (v) i d , drain current (a) 0.01 0.1 1 10 100 1 10 100 1000 * v gs > minimum v gs at which r d s (on) i s s pecied operation in thi s area limited by r d s (on) bvd ss limited t c = 25 c t j = 150 c s ingle pul s e limited by r d s (on) * 100 s 1 m s 10 m s t j , case temperature (c) i d , drain current (a) 25 50 75 100 125 150 1 2 3 4 5 6 0 t j , junction temperature (c) v ds , drain-to-source - 60 0 160 brakdown voltage (v) - 40 - 20 20 40 60 80 100 120 140 475 500 525 550 575 600 625 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective tran s ient thermal impedance pul s e time ( s ) duty cycle = 0.5 0.1 0.05 s ingle pul s e 0.2 0.02
fig. 12 - switching time test circuit fig. 13 - switching time waveforms fig. 14 - unclamped inductive test circuit fig. 15 - unclamped inductive waveforms fig. 16 - basic gate charge waveform fig. 17 - gate charge test circuit pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - SIHD5N50D d series power mosfet www.freescale.net.cn 5 / 9 SIHD5N50D www.vishay.com vishay siliconix s12-0690-rev. a, 02-apr-12 5 document number: 91499 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12 - switching time test circuit fig. 13 - switching time waveforms fig. 14 - unclamped inductive test circuit fig. 15 - unclamped inductive waveforms fig. 16 - basic gate charge waveform fig. 17 - gate charge test circuit pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
fig. 18 - for n-channel p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd SIHD5N50D d series power mosfet www.freescale.net.cn 6 / 9 SIHD5N50D www.vishay.com vishay siliconix s12-0690-rev. a, 02-apr-12 6 document number: 91499 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 18 - for n-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91499 . p.. period d/dt iode recovery dv/dt ripple ody diode forward drop reapplied voltage rever s e recovery current ody diode forward current v s 1 v a s river gate drive ..t. l s waveform ..t. v s waveform nductor current p.. period peak io d e recovery d v/ d t test ircuit v dv/dt controlled by r g river s ame type a s ..t. s controlled by duty factor ..t. device under te s t ..t. ircuit layout con s ideration s ow s tray inductance round plane ow leakage inductance current tran s former r g ote a. v s v for logic level device s v
to-252aa (high voltage) notes 1. package body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973 SIHD5N50D d series power mosfet www.freescale.net.cn 7 / 9 document number: 91344 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-252aa (high voltage) notes 1. package body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - t 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973
recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index SIHD5N50D d series power mosfet www.freescale.net.cn 8 / 9 application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
disclaimer material category policy SIHD5N50D d series power mosfet www.freescale.net.cn all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. freestyle intertechnology, inc., its affiliates, agents, and employees, and all persons acting on it s or their behalf (collectively, ?freestyle?), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. freestyle makes no warranty, representation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on freestyle?s knowledge of typical requirements that are often placed on freestyle products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customer?s responsib ility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customer?s technical experts. product specifications do not expand or otherwise modify freestyle?s terms and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, freestyle products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the freestyle product could result in personal injury or death. customers using or selling freestyle products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold freestyle and its distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay freestyle intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the european parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some freestyle documentation may still make reference to rohs directive 2002/95/ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. 9 / 9 legal disclaimer notice www.vishay.com vishay revision: 12-mar-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, ?vishay?), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishay?s knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customer?s responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customer?s technical experts. product specifications do not expand or otherwise modify vish ay?s terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products no t expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale , including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding th e design or manufacture of the part. please contact authorized vishay personnel t o obtain written terms and conditions regardin g products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu.
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